make is a tool responsible for generating binary and other non-source
files of a program from the program’s source.
make can be used to compile source code of any language.
- enables user to build and install software without knowing the details of that specific software
- compiles source files as needed. can relate to hot-reloading.
makeis also capable of installing and uninstalling packages.
A Makefile contains instructions for
make to run. A series of
instructions are known as a rule. A Makefile also describes relationship
among files.Example of a simple rule:
target … : prerequisites … recipe … …
- target is usually the name of the file that is generated by a program.
This file generally is an executable or object file.
A target can also be the name of an action to carry out, sucj as
- prerequisite is a file that is used as input to create target.
- recipe is an action
makeuses tab for indentation. Failing to use it would throw an error
- by default, starts with first target. also known as default goal
makemust process rules the target depends on
- recompilation is done only when target is older than source files; or when target does not exists
- allows storing data in variable
- variable declaration example:
objects = main.o kbd.o.
objects = main.o kbd.o edit : $(objects) cc -o edit $(objects) main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c clean : rm edit $(objects)
make has an implicit rule for updating
.o file from a correspondingly
.c file using
cc -c command.
.c file is used through implicit rule, it is also added to the
list of prerequisites. Hence,
.c files can be omitted from
objects = main.o kbd.o command.o display.o edit : $(objects) cc -o edit $(objects) main.o : defs.h kbd.o : defs.h command.h command.o : defs.h command.h display.o : defs.h buffer.h .PHONY : clean clean : rm edit $(objects)
when using implicit rules, an alternate way of writing Makefile can be used. in this type of Makefile, entries are grouped by their prerequisites instead of by their targets
objects = main.o kbd.o command.o display.o edit : $(objects) cc -o edit $(objects) $(objects) : defs.h kbd.o command.o files.o : command.h display.o : buffer.h
make can clean a given directory. for that Makefile should have an
explicit .PHONY target.
maketo confuse it with an actual file target and causes it to continue in spite of errors from
clean can be executed by passing it as an arg to
clean should not be placed at top of the Makefile. Otherwise it would
become global target and will be executed by default.
.PHONY : clean clean : -rm edit $(objects)
what a Makefile may contain
- variable definitions
- directives (instruction for make to do something special while
reading the makefile)
- Reading another makefile
- deciding whether to ignore a part of Makefile
- comments (starts with
#). for multiline comment, a backslash should be used at breakpoints
- Long lines can be splitted into multiple lines using backslash
Including other Makefile
makecan read multiple Makefiles which are added using
includedirective. filenames can contain shell file name patterns.
- if included file is empty,
include foo *.make $(bar)
- when path of file is not absolute, and the file is not found in current dir,
makelooks for it in some other places(in following order).
- dirs mentioned with -I flag (
- dirs mentioned with -I flag (
- NOT_FOUND warnings/errors can be supressed with
- env variable
MAKEFILEScan be used to preload other makefiles (spearated by whitespace)